Per CPU data

Since this will be a SMP port, I need some to determine which CPU this is. On sane architectures this is easy since the CPU has registers to help figure that out. But for some reason, the MIPS architects left that out. So I'm going to take a suggestion and rework it a bit.

For each CPU, I'm going to allocate a 64KB contiguous and aligned region of memory and wire it into the TLB at -8000 hex (this will be signed extended to 0xffff8000 in 32 bit kernels and 0xfffffffffff8000 in 64 bit kernels). The advantage of this is you can load and address of per-cpu stuff into a register with one instruction using a signed offset with $0. The 32KB below -8000 will be the interrupt/exception stack for that CPU.

Note that for other CPUs to access the per-cpu data, it will be references using KSEG0 which will require all such blocks to be the first 256MB of RAM (which shouldn't be a problem).